In recent years, in the progress toward higher functions, reduction in size, and reduction in weight of electronic devices, there have been requests for reduction in size, increase in number of pins, and finer pitches of external terminals, with respect to semiconductor packages, so that demands for high density wiring boards have been increasing more and more. To this end, LSIs have been directly mounted on printed wiring boards, or CSP (Chip Size Package) or BGA (Ball Grid Array) has been mounted on printed wiring boards. And, for coping with higher densification, multilayer wiring boards produced by a buildup wiring technique wherein wiring layers and vias are stacked in multilayers on a board, serving as a core, via electrically insulating layers one by one, have been used as printed wiring boards.
The multilayer wiring board is provided with through holes each electrically connecting between conductors on upper and lower sides of the board, and uses, as a core board, a double-sided board having low density wiring produced by the subtractive method or the additive method and then multilayered. However, the conventional through hole is formed by drilling so that there is limitation about a hole diameter in view of dimensional minimization, and further, it is a penetrating hole, and therefore, there has been a problem that, in the multilayer board, the hole not only connects between the desired two conductors, but also perforates a conductor layer of another portion, which is primarily unrequited, and therefore, wiring can not be formed at that portion to limit the degree of freedom for wiring design. Further, the electrical connection by means of plating inside the through hole has raised a problem in reliability following reduction in conductor line width.
In view of this, various wiring methods have been proposed and carried out as manufacture methods of core boards, and multilayer wiring boards obtained by forming wiring layers on these core boards have been used (e.g. Laid-open Unexamined Patent Publication No. H5-144978, and Laid-open Unexamined Patent Publication No. H11-345933).
However, along with the dimensional minimization and the narrowing of pitches of wiring of the core boards, finer line widths have been required also for wiring of multilayer wiring layers provided on the core boards by the buildup method, so that demands for the narrowing of pitches and the high density wiring have been increasing more and more. Consequently, there has been a problem that the multilayer wiring boards formed with the wiring layers on the known conventional core boards by the conventional process can not cope with the demands for dimensional minimization for required electrical properties and high density wiring.
Further, following the high density mounting caused by the narrowing of pitches and the increase in number of pins, for electrical connection between wiring boards and semiconductor chips or the like, the flip chip technique for face-down mounting the semiconductor chip, or the like has been used instead of the conventional wire bonding technique. In the multilayer wiring boards using the flip chip technique, there has been a problem that if void portions remain at through holes connecting between boards, occurrence of cracks or disconnection due to thermal shock is liable to be induced, thereby to lower the reliability.
Further, there has been a problem that, following reduction in hole diameter of the through holes for the high density mounting, a diameter of a land provided at an opening portion of the through hole is also reduced, so that wiring connection between wiring boards becomes difficult. Further, there has also been a problem that, upon semiconductor chip mounting where solder bumps are formed on the board, since mounting pads are small, it becomes difficult to supply solder to the small-diameter pads.
On the other hand, in recent years, with respect to semiconductor chips, in the progress of higher densification of integrated circuit elements such as ICs and LSIs (hereinafter, collectively referred to as LSI), the operation speeds thereof have been increasing every year. There is a problem that when the operation speed of LSI increases, switching noise generated inside the semiconductor chip causes an operation failure of LSI. For reducing the switching noise, it is effective to dispose a capacitor between a power bus line and a grounding bus line.
If capacitors are disposed on a wiring board as external components, connection distances between these components and a semiconductor chip become long to cause a large wiring inductance, so that the effect of the capacitors becomes insufficient. Therefore, the capacitor is required to be located as close to LSI as possible, and is desired to be directly formed on the semiconductor chip. However, in this case, an area of the semiconductor chip increases to raise cost. Further, since the manufacturing process becomes complicated and long, there has been a problem that the yield of semiconductor chips themselves is lowered due to failure of capacitors.
For coping with these problems, it has been proposed to incorporate capacitors in an intermediate board (interposer or semiconductor chip carrier) that is used when mounting a semiconductor chip onto a wiring board (e.g. Laid-open Unexamined Patent Publication No. H8-148595 or Laid-open Unexamined Patent Publication No. 2001-326298).
Alternatively, there has been proposed a method of incorporating capacitors in a multilayer wiring layer stacked on a core board (e.g. Laid-open Unexamined Patent Publication No. H7-30258).
However, a semiconductor device shown in Laid-open Unexamined Patent Publication No. H8-148595 is configured that a chip carrier made of glass ceramic and having thick film capacitors is connected to a base board. Therefore, it is difficult to thin a dielectric layer so that there is a limit in property of the capacitor. Laid-open Unexamined Patent Publication No. 2001-326298 shows a structure provided with an interposer made of ceramic and having capacitors. However, there has been a problem in the method employing the interposer that a material and a thickness of a dielectric layer of the capacitor, and a position, a size, and the like of the capacitor should be determined in advance.
With respect to a circuit board with built-in capacitors described in Laid-open Unexamined Patent Publication No. H7-30258, there has been a problem that since the built-in capacitors are buried in a multilayer wiring layer, sizes of electrodes are also fixed, and a position, a size, and the like of the capacitor should be determined in advance, so that it is not possible to flexibly cope with a change in specification. Further, there has been a problem that the manufacturing process of the conventional circuit board having the multilayer wiring with the built-in capacitors is long to thereby lower the manufacturing yield.